Non-volatile memory (NVM) is a type of computer memory that retains stored information even after power cycling—powering a device off and then on again. In contrast, volatile memory is a type of computer memory that requires power to maintain the stored information—when the power is off or interrupted, the stored data is lost. A traditional type of non-volatile memory is a hard disk drive (HDD), which stores and accesses data using one or more rotating disks (platters) coated with magnetic material.
Another type of storage memory is a solid state drive (SSD), which differs from a HDD in that digital data is stored and retrieved using electronic circuits, without any moving mechanical parts. SSDs can be used based on both volatile memory, such as dynamic random-access memory (DRAM) or static random access memory (SRAM), or non-volatile memory, such as NAND flash memory. The standard NAND flash memory can be Single Level Cell (SLC) or Multi Level Cell (MLC), including enterprise MLC (eMLC), Triple Level Cell (TLC) and Quadratic Level Cell (QLC). SSDs with NAND flash memory have been widely adopted for use in consumer products and in enterprise data centers.
A typical NAND flash memory SSD includes a memory controller and a number of NAND flash memory devices. The memory controller communicates with a host through the host interface on one side and with the NAND flash memory devices through multiple interfaces, commonly referred to as channels, on the other side. A channel controller accesses multiple NAND flash memory devices through a common shared bus interface (a channel). While each NAND flash memory device coupled to a channel may operate independently at the same time, only a single command or data payload may be transferred between the channel controller and one of the NAND flash memory devices at a given time on the shared channel. Thus communications between the channel controller and the NAND flash memory devices must be multiplexed in time. With each new generation of NAND flash memory devices, more features, larger capacities, and new timing requirements are introduced. The timing requirements, including maximum block erase times, maximum erase suspension times, and maximum page write times, should be satisfied to maintain the health of the NAND flash memory devices for their expected lifetimes. New generations of SSDs may also include larger numbers of NAND flash memory devices per channel, for example 8, 16, or more. As NAND flash memory devices per channel become more numerous and complex, the channel controller's task to time multiplex commands and data on the channel becomes more challenging. Thus there is a need for a system and method for channel time management in solid state storage drives.